The complexity, capacity, and intelligence of computer systems is ever evolving. Industry standards are often developed in an attempt to provide a degree of compatibility between computer systems and/or their functional components. For instance, various processor architectures are known in the art, such as the PA-RISC family of processors developed by HEWLETT-PACKARD Company (“HP”), INTEL Corporation's (INTEL) architecture (IA) processors (e.g., the well-known IA-32 and IA-64 processors), and the like. As is well-known, IA-64 is a 64-bit processor architecture co-developed by HP and INTEL, which is based on Explicitly Parallel Instruction Computing (EPIC). ITANIUM is the first microprocessor based on the IA-64 architecture. Developed under the code name of MERCED, ITANIUM and its underlying architecture provide a foundation for software for various platforms, including without limitation the server and high-end workstation platforms.
In addition to supporting a 64-bit processor bus and a set of 28 registers, the 64-bit design of ITANIUM allows access to a very large memory (VLM) and exploits features in EPIC. Features of ITANIUM provide advances in the parallel processing handling of computer instructions known as predication and speculation. An additional ITANIUM feature includes a Level 3 (L3) cache memory, to supplement the current L1 and L2 cache memories found in most of today's microcomputers. Other IA-64 microprocessors have followed ITANIUM, including those having the code names of MCKINLEY and MADISON.
Processor architecture generally comprises corresponding supporting firmware. For example, the IA-64 processor architecture comprises such supporting firmware as Processor Abstraction Layer (PAL), System Abstraction Layer (SAL), and Extended Firmware Interface (EFI). Such supporting firmware may enable, for example, the Operating System (OS) to access a particular function implemented for the processor. For instance, the OS may query the PAL as to the size of the cache implemented for the processor, etc. Other well-known functions provided by the supporting firmware (SAL, EFI) include, for example: (a) performing input/output (“I/O”) configuration accesses to discover and program the I/O Hardware (SAL_PCI_CONFIG_READ and SAL_PCI_CONFIG_WRITE); (b) retrieving error log data from the platform following a Machine Check Abort (MCA) event (SAL_GET_STATE_INFO); (c) accessing persistent store configuration data stored in non-volatile memory (EFI variable services: GetNextVariableName, GetVariable and SetVariable); and accessing the battery-backed real-time clock/calendar (EFI GetTime and SetTime). Accordingly, the supporting firmware, such as the PAL, is implemented to provide an interface to the processor(s) for accessing the functionality provided by such processor(s). Each of those interfaces provide standard, published procedure calls that are supported.
Generally, if new functionality is provided in a processor, its supporting firmware is revised to support such new functionality. For example, if a new cache is implemented in a processor, its supporting firmware, such as its PAL, is typically modified to support the new cache, e.g., by modifying the PAL interface to support additional procedure calls relating to the new cache. Further, for certain changes to a processor, the OS with which the processor is to be used may need to be modified to recognize those changes. For instance, the OS may need to have new procedure calls implemented for accessing new features implemented in a processor. Thus, as developers expand the functionality of their processors, they generally implement new supporting firmware and/or modify the OS to recognize the new functionality.